The present invention is directed to semiconductor processes and devices.
Since the early days when Dr. Jack Kilby at Texus Instrument invented the integrated circuit, scientists and engineers have made numerous inventions and improvements on semiconductor devices and processes. The last five decades or so have seen a significant reduction in semiconductor sizes, which translate to ever increasing processing speed and decreasing power consumption. And so far, the development of semiconductor has generally followed Moore's Law, which roughly states that the number of transistors in a dense integrated circuit doubles approximately every two years. Now, semiconductor processes are pushing toward below 20 nm, where some companies are now working on 14 nm processes. Just to provide a reference, a silicon atom is about 0.2 nm, which means the distance between two discrete components manufactured by a 20 nm process is just about a hundred silicon atoms.
Manufacturing semiconductor devices has thus become more and more challenging and pushing toward the boundary of what physically possible. Huali Microeletronic Corporation™ is one of the leading semiconductor fabrication companies that has focused on the research and development of semiconductor devices and processes.
Fin field-effect transistor (FinFET) devices include a transistor architecture that uses raised source-to-drain channel regions, referred to as fins. A FinFET device can be built on a silicon-on-insulator (SOI) substrate, where a semiconductor material, such as silicon, is patterned into a fin-like shape and functions as the channel of the transistor. A gate can be wrapped around and over the fin. A double or dual gate structure includes a gate oxide and gate contact formed on two sides of the channel. A 3D tri-gate FinFET includes a gate structure wrapped on three sides of a fin. Unlike a 2D planar FET, in a 3D FinFET device, a channel is formed perpendicular to the upper surface of the semiconducting substrate, thereby reducing the physical size of the FinFET device. Thus, the 3D tri-gate FinFET structure effectively overcomes the transistor size problem of a FinFET device and improves device performance. However, compared to a 2D planar FinFET, the three gate and vertical fin structure of the 3D tri-gate FinFET device can increases the difficulty of integrating 3D tri-gate FinFET devices.
For example, etching of a nitride spacer adjacent to the gate is one of the critical challenges in FinFET device integration process. A common etching method of the nitride spacer is plasma etching. Etchants that can be used in a plasma process for removing polycrystalline silicon include HC1, HBr, HI, and C12, alone or in combination with each other and/or one or more of He, Ar, Xe, N2, and 02. A suitable etchant that can be used for removing a silicon oxide is a plasma comprising CF4/CHF3, or CF4/CH2F2. A suitable etchant for removing silicon nitride is a plasma comprising CF4/HBr. In operation of the plasma process, plasma gases can be flowed into internal chamber and converted into plasma by energy input from a reaction coil. An RF bias can be generated at a substrate to draw plasma components to a surface of substrate to etch a material at such surface. As the etch proceeds, the concentration of the evolved reaction products and/or etchant gases can be monitored. Monitoring of the etchant debris can be accomplished by, for example, spectroscopic methods, including, for example, ultraviolet-visible spectroscopy and mass spectrometry.
A further understanding of the nature and advantages of various embodiments may be realized by reference to the following figures. In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.